1. Field of the Invention
The disclosed invention generally relates to configurable gate arrays (CGA's), and is particularly directed to a configurable gate array which utilizes hierarchical cluster levels.
2. Description of Background Art
In the semiconductor industry two principal design approaches are utilized in the design and manufacture of integrated circuits; namely, custom logic and semicustom logic.
Custom integrated circuits typically involve expensive custom design to provide a one-of-a-kind integrated circuit for specific functions. While extremely costly to design, such custom integrated circuits are typically intended for large quantity production.
A semicustom integrated circuit generally utilizes a "standardized" integrated circuit chip which includes a plurality of individual circuit elements arranged in arrays. The integrated circuit chip is then adapted to provide desired electrical functions by selectively interconnecting the circuit elements. For example, such interconnections may be accomplished by appropriate metalization processing. A "standardized" integrated circuit chip is basically a foundation on which the desired logic functions are achieved by selective interconnections of the circuit elements.
One form of semicustom logic design and manufacture is based on integrated circuit gate arrays produced by different companies. Generally, an integrated circuit gate array includes a plurality of individual logic gates arranged in arrays which typically are not interconnected. The desired logic functions are then achieved by selective interconnection of the inputs and outputs of the gates. As the number of gates in a gate array increases, i.e., as gate density increases, interconnection routing rapidly becomes more complex and difficult. As a result of interconnection difficulties the gate utilization factor, i.e., the percentage of gates actually utilized, decreases.
While several major types of configurable gate arrays have been developed in attempts to improve routability and utilization such configurable gate arrays currently have substantial disadvantages and limitations.
For example, in channel routed arrays, wherein channels for interconnections are provided between groups of gates, an upper limit of about 3,500 gates is reached. Moreover, routing distances become excessively long.
In prior art gate arrays wherein gates are uniformly distributed, routing tends to be unstructured and limited by spacing between the gates. It is believed that such a uniformly distributed gate array has an upper limit of about 1,000 gates.
In prior art arrays wherein gates are not uniformly distributed, routing also tends to be unstructured and limited by the widths of the routing channels.
Another type of prior art gate array includes logic gates and dedicated "macros" which are functional circuits (e.g., flip-flops) made from preconnected logic gates. Since the circuit elements for the macros are dedicated to specific functions, such circuit elements can be efficiently packed. Such arrays have an upper limit of about 6,000 gates. Increasing the number of gates would require larger macros which would limit the potential applicability of such an array. Thus, the gates/macros approach is believed to be self-limiting.
As is readily evident from the foregoing described prior art, interconnection routing and space constraints present significant limitations relative to increasing gate density while maintaining a high level of gate utilization.